A processor typically contains some type of storage system for temporarily storing data during processor operations. One of the temporary storage components embedded in the processor is referred to as a “register file.” A register file usually includes a design that is unique to the specific processor. For instance, based on the design of the processor, register files may include multiple ports for allowing parallel accesses to data stored in the register file so that multiple reading and/or writing operations can be performed simultaneously. Currently, multi-port register files are typically configured with two or four ports. However, register files with a different number of ports have been contemplated.
Some of the ports of a multi-port register file are used as read ports and others are used as write ports. For example, a six-port register file may include two write ports and four read ports. Each port typically includes a number of “bitlines” leading to a corresponding number of input flip-flops or output flip-flops. From outside the register file, input flip-flops clock data into the register file via write bitlines. Data output from the register files is transmitted along read bitlines, and output flip-flops clock the data from the read bitlines to other components of the processor.
The number of bitlines and corresponding input and output flip-flops for each port is equal to the number of bits of the size of a data value that the register file is configured to handle. In an example of a data value having eight bits, each port of the multi-port register file will have eight bitlines leading to eight corresponding flip-flops. In order to increase data access speed, all eight bits of an eight-bit data value can be transferred in parallel along the parallel bitlines of a particular port between the flip-flops and eight corresponding “bitcells” within the register file. The data values from input flip-flops can be written to the bitcells of the register file and data values in the bitcells can be read to output registers. In a writing operation, the data values are transferred along the eight respective write bitlines of a particular input port from the input flip-flops to the bitcells. In a reading operating, the data values are transferred along eight respective read bitlines of a particular output port from the bitcells to the output flip-flops.
FIG. 1 is a schematic diagram of a conventional bitcell 10 for a six-port register file. The bitcell 10 includes two write bitlines WBL0, WBL1 and four read bitlines RBL0, RBL1, RBL2, RBL3. The bitcell 10 contains a driver 12, which drives all four read bitlines. The bitcell 10 also contains an inverter 14, also referred to herein as a keeper, connected in parallel with the driver 12 for transmitting signals in a direction opposite from the direction in which the driver 12 transmits signals. The write bitlines WBL0, WBL1 also contain drivers 16 and 18. Each of the write bitlines and read bitlines includes a transmission gate 20, i.e. a field effect transistor (FET), for controlling the transmission of data along the respective bitline. Each transmission gate 20 receives a control signal at its gate terminal for opening or closing the transmission gate 20. For example, on the read bitlines RBL0, RBL1, RBL2, and RBL3, the four respective FETs receive read wordline control signals RDWL0, RDWL1, RDWL2, and RDWL3. Also, the FETs 20 on the write bitlines WBL0 and WBL1 receive write wordline control signals WRWL0, WRWL1 on their respective gates.
This conventional bitcell 10 is configured such that its driver 12 drives all four read bitlines by itself, which can have several disadvantages. To maintain a fast processor speed, the driver 12 must be relatively large in order to be capable of driving the read bitlines. Since this element must be large, it is very likely that the conventional bitcell 10 will suffer from crosstalk coupling, in which the strong driving signals are coupled to the branch of the keeper 14 in an undesirable manner. Crosstalk coupling can also occur between the adjacent bitlines RBL0, RBL1, RBL2, RBL3. In addition, since the driver 12 is large, the size of the drivers 16 and 18 on the write bitlines will also need to be relatively large in order to drive the large driver 12 of the bitcell 10.
Another drawback of the conventional bitcell 10 is that the load driven by the driver 12 will vary depending on the status of the transmission gates 20. If the number of read wordlines RDWL0, RDWL1, RDWL2, RDWL3 that open the FET gates 20 is high, then the driver 12 will see a larger load. For instance, when a gate is closed, the driver 12 only sees one side of the FET 20 and when a gate is open, the driver 12 sees both sides. Therefore, the load can vary greatly based on the number of opened gates. As a result, the access time of the register file will vary, which creates a condition that makes it difficult to meet stringent timing specifications. Moreover, if timing specifications are not met, then the variable load condition may require that an additional compensation circuitry be added to yield a fixed access time. Not only does a compensation circuitry involve additional work to create it, but also such a circuit adds more delay to the output. These and other disadvantages of the prior art are overcome by the improved bitcell design as described below.